Univ. of Aizu

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@
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Dr. Yukihide Kohira, Associate Professor

kohira Computer Logical Design Laboratory

Office: 102-C, Research Quadrangles
Tel: +81-242-37-2536
Email: koriha

URL: www.u-aizu.ac.jp/~kohira/


Education D.Eng., Tokyo Institute of Technology

Teaching
Courses
  • Semiconductor Devices
  • Logic Circuit Design
  • Advanced Logic Circuit Design (Exercise)
  • Courses for the Information Technology Examination

Research
Interests
  • VLSI design automation
  • VLSI layout algorithms
  • Combinational algorithms

Recent Projects
  • Design Automation Methodology for LSI chips with Programmable Delay Elements (competitive funds from UoA)

Selected
Publications
  • Yukihide KOHIRA, Atsushi TAKAHASHI, gA Fast Gate-Level Register Relocation Method for Circuit Size Reduction in General-Synchronous Frameworkh, IEICE Trans. Fundamentals, Vol.E91-A, No.10, pp.3030-3037, 2008.
  • Yosuke TAKAHASHI, Yukihide KOHIRA, Atsushi TAKAHASHI, gA Fast Clock Scheduling for Peak Power Reduction in LSIh, IEICE Trans. Fundamentals, Vol.E91-A, No.12, pp.3803-3811, 2008.
  • Yukihide KOHIRA, Shuhei TANI, Atsushi TAKAHASHI, gMinimization of Delay Insertion in Clock Period Improvement in General-Synchronous Frameworkh, IEICE Trans. Fundamentals, Vol.E92-A, No.4, pp.1106-1114, 2009.
  • Yukihide KOHIRA, Suguru SUEHIRO, Atsushi TAKAHASHI, gA Fast Longer Path Algorithm for Routing Grid with Obstacles using Biconnectivity based Length Upper Boundh, IEICE Trans. Fundamentals, Vol.E92-A, No.12, pp.2971-2978, 2009.
  • Yukihide KOHIRA, Atsushi TAKAHASHI, gCAFE router: A Fast Connectivity Aware Multiple Nets Routing Algorithm for Routing Grid with Obstaclesh, IEICE Trans. Fundamentals, Vol.E93-A, No.12, pp.2380-2388, 2010.