Univ. of Aizu

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Dr. Hiroshi Saito, Senior Associate Professor

hiroshis Computer Organization Laboratory

Office: 206-C, Research Quadrangles
Tel: +81-242-37-2576
Email: hiroshis

URL: www.u-aizu.ac.jp/~hiroshis/


Education Ph.D., The University of Tokyo

Teaching
Courses
  • Logic Circuit Design
  • Advanced Logic Circuit Design
  • Computer-aided Design of Integrated Circuits I
  • Computer-aided Design of Integrated Circuits II

Research
Interests
Automated design of VLSI asynchronous circuits, and hardware/software co-design and formal ratification of System LSI.

Selected
Publications
  • Naohiro Hamada, Yuuki Shiga, Takao Konishi, Hiroshi Saito, Tomohiro Yoneda, Cris Myers, and Takashi Nanya, "A Behavioral Synthesis System for Asynchronous Circuits with Bundled-data Implementation", IPSJ Transaction on System LSI Design Methodology, no.2, pp.67--79, Feburary 2009.
  • Hiroshi Saito, Naohiro Hamada, Nattha Jindapetch, Tomohiro Yoneda, Cris Myers, and Takashi Nanya, "Scheduling Methods for Asynchronous Circuits with Bundled-Data Implementations Based on the Approximation of Start Times", IEICE Transaction, vol.E90-A, no.12, pp.2790--2799, December 2007.
  • Hiroshi Saito, Hiroshi Nakamura, Masahiro Fujita, and Takashi Nanya, "Logic Optimization of Asynchronous Speed-Independent Circuits Using Transduction Methods", IPSJ Transaction, vol.45, no.5, pp.1289--1299, May 2004.
  • Hiroshi Saito, Alex Kondratyev, Jordi Cortadella, Luciano Lavagno, Alex Yakovlev, and Takashi Nanya, "Design of Asynchronous Controllers with Delay Insensitive Interface", IEICE transaction, vol.E85-A, no.12, pp.2577-2585, December 2002.