Univ. of Aizu

CE Division


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Dr. Abderazek Ben Abdallah, Professor

benab A​d​a​p​t​i​v​e​ ​S​y​s​t​e​m​s​ ​L​a​b​o​r​a​t​o​r​y

Office: 202-A, Research Quadrangles
Tel: +81-242-37-2574
Email: benab
URL: www.u-aizu.ac.jp/~benab/

Education Ph.D., Univ. of Electro-Communications, Japan


My main research effort involves the design of future generations of high-performance and low-power computer systems. Currently, I am focusing on System Design and its Design Support for Multicore Systems, Network-on-Chip Design and Analysis, and Virtualization on Multicores Systems and Cloud Computer/Computing.

  • In-Body Wireless Sensor Network System for Elderly Monitoring
  • OASIS: Basic Network-on-Chip

  • A. Ben Abdallah, M. Masuda, A. Canedo, K. Kuroda,"Natural Instruction Level Parallelism-aware Compiler for High-Performance Processor Architecture", Accepted, To appear in the Journal of supercomputing, 2011.
  • A. Canedo, A. Ben Abdallah, and M. Sowa, "Efficient Compilation for Queue Size Constrained Queue Processors", The Journal of Parallel Computing, Vol.35, pp. 213-225, 2009.
  • A. Ben Abdallah, A. Canedo, T. Yoshinga, and M. Sowa, "The QC-2 Parallel Queue Processor Architecture", Journal of Parallel and Distributed Computing, Vol. 68, No. 2, pp. 235-245, 2008.
  • A. Ben Abdallah, T. Yoshinaga, and M. Sowa, High-Level Modeling and FPGA Prototyping of Produced Order Parallel Queue Processor Core, Journal of supercomputing, Vol. 38, Number 1, pp. 3-15, 2006
  • A. Ben Abdallah, Mudar Sarem, and M. Sowa, "Dynamic Fast Issue Mechanism (DFI) for Dynamic Scheduled Processors", IEICE transactions on Fundamental of Electronics, Communications and computer Science, Vol. E83-A No.12 pp.2417-2425, Dec. 2000