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Embedded Systems


Introduction | Research Labs | People | Publications


Introduction

  • Reconfiguratble Systems
  • Wireless Sensor Networks
  • VLSI
  • HW/SW Codesign
  • Hardware acceleration of algorithms
  • Formal verification
  • System modeling
  • Video analysis algorithms

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Research Labs



People

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Recent Publications

  • R. Kawano, and T. Miyazaki, "Simultaneous Optimization for Dynamic Sensor Function Allocation and Effective Sensed Data Aggregation in Wireless Sensor Networks," International Journal of Future Generation Communication and Networking (IJFGCN), Vol.2, No. 4, pp.15-28, Dec. 2009
  • T. Miyazaki, R. Kawano, Y. Endo, and D. Shitara, "A Sensor Network for Surveillance of Disaster-hit Region," Proc. IEEE International Symposium on Wireless and Pervasive Computing (ISWPC2009), pp. 1-6, Melbourne, February 2009.
  • T. Miyazaki, "Boolean Formulation for Sensor Allocation Problem and Its Effective Solver," Proc. ACM/IFIP/USENIX MidSens'06 (International Workshop on Middleware for Sensor Networks), pp. 46-54, Melbourne Australia, Nov. 2006.
  • T. Miyazaki, A. Takahara, T. Murooka, M. Katayama, T. Ichimori, K. Shrakawa, A. Tsutsui, and K. Fukami, ``PROTEUS-Lite Project: Dedicated to Developing a Telecommunication-oriented FPGA and its Applications,'' IEEE Trans. on VLSI Systems, Vol. 8, No. 4, pp.401-414, August 2000.
  • T. Miyazaki (Tanaka), T. Kobayashi and O. Karatsu, ``HARP: Fortran to Silicon,'' IEEE Trans. on CAD, Vol. 8, No. 6, pp.649-660, June 1989.
  • T. Tsukahara, H. Ito, and T. Tsushima, "Evolution of Low-Power CMOS RF Transceivers," 2010 Asia-Pacific Radio Science Conference (AP-RSAC), CBDFK-1, Toyama, Japan, Sept. 2010. [Invited Paper]
  • T. Tsukahara, T. Tsushima, and H. Ito, "Evolution of Transceiver Architectures toward Software-Defined and Cognitive Radios," 2010 Int'l Conference on Solid State Devices and Materials (SSDM), pp. 99-100, Tokyo, Japan, Sept. 2010. [Invited Paper]
  • PvAuCMOS RFH݌vvAۑPA2009N11sD@ (T. Tsukahara, gDesign of CMOS RF Circuits,h MARUZEN, Nov. 2009.) [ISBN: 978-4-621-08203-4]
  • T. Tsukahara, gRF CMOS Circuits– Overview and Perspective,h 2007 Intfl Conference on Solid State Devices and Materials (SSDM), pp. 752-753, Tsukuba, Japan, Sept. 2007. [Invited Paper
  • M. Ugajin, A. Yamagishi, J. Kodate, M. Harada, and T. Tsukahara, gA 1-V CMOS SOI Bluetooth RF Transceiver Using LC-Tuned and Transistor-Current-Source Folded Circuits,h IEEE J. Solid-State Circuits, vol. 39, no. 4, pp. 569-576, April 2004.
  • Naohiro Hamada, Yuuki Shiga, Takao Konishi, Hiroshi Saito, Tomohiro Yoneda, Cris Myers, and Takashi Nanya, "A Behavioral Synthesis System for Asynchronous Circuits with Bundled-data Implementation", IPSJ Transaction on System LSI Design Methodology, no.2, pp.67--79, Feburary 2009.
  • Hiroshi Saito, Naohiro Hamada, Nattha Jindapetch, Tomohiro Yoneda, Cris Myers, and Takashi Nanya, "Scheduling Methods for Asynchronous Circuits with Bundled-Data Implementations Based on the Approximation of Start Times", IEICE Transaction, vol.E90-A, no.12, pp.2790--2799, December 2007.
  • Hiroshi Saito, Hiroshi Nakamura, Masahiro Fujita, and Takashi Nanya, "Logic Optimization of Asynchronous Speed-Independent Circuits Using Transduction Methods", IPSJ Transaction, vol.45, no.5, pp.1289--1299, May 2004.
  • Hiroshi Saito, Alex Kondratyev, Jordi Cortadella, Luciano Lavagno, Alex Yakovlev, and Takashi Nanya, "Design of Asynchronous Controllers with Delay Insensitive Interface", IEICE transaction, vol.E85-A, no.12, pp.2577-2585, December 2002.
  • Yukihide KOHIRA, Atsushi TAKAHASHI, gA Fast Gate-Level Register Relocation Method for Circuit Size Reduction in General-Synchronous Frameworkh, IEICE Trans. Fundamentals, Vol.E91-A, No.10, pp.3030-3037, 2008.
  • Yosuke TAKAHASHI, Yukihide KOHIRA, Atsushi TAKAHASHI, gA Fast Clock Scheduling for Peak Power Reduction in LSIh, IEICE Trans. Fundamentals, Vol.E91-A, No.12, pp.3803-3811, 2008.
  • Yukihide KOHIRA, Shuhei TANI, Atsushi TAKAHASHI, gMinimization of Delay Insertion in Clock Period Improvement in General-Synchronous Frameworkh, IEICE Trans. Fundamentals, Vol.E92-A, No.4, pp.1106-1114, 2009.
  • Yukihide KOHIRA, Suguru SUEHIRO, Atsushi TAKAHASHI, gA Fast Longer Path Algorithm for Routing Grid with Obstacles using Biconnectivity based Length Upper Boundh, IEICE Trans. Fundamentals, Vol.E92-A, No.12, pp.2971-2978, 2009.
  • Yukihide KOHIRA, Atsushi TAKAHASHI, gCAFE router: A Fast Connectivity Aware Multiple Nets Routing Algorithm for Routing Grid with Obstaclesh, IEICE Trans. Fundamentals, Vol.E93-A, No.12, pp.2380-2388, 2010.
  • Yukihiro Yoshida, Koushi Yamaguchi, Yuichi Yaguchi, Yuichi Okuyama, Ken-ichi Kuroda and Ryuichi Oka, "Acceleration of Two-Dimentional Continuous Dynamic Programming by Memory Reduction and Parallel Processing," IADIS International Conferrence Applied Computing 2010, pp61-68, Timisoara, Romania, Oct. 2010.
  • Fumiko OHORI, Yuichi OKUYAMA, Junji KITAMICHI, Kenichi KURODA, and Tsuyoshi HAMADA, "Evaluation of an Image Filtering Algorithm using the Particle Interaction Accelerator on FPGA," The 24th International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC 2009), July 2009.
  • Takahiro Machino, Shin-ya Iwazaki, Yuichi Okuyama, Junji Kitamichi, Ken-ichi Kuroda, and Ryuichi Oka, "Optimizing Two-Dimensional Continuous Dynamic Programming for Cell Broadband Engine Processors," Japan-China Joint Workshop on Frontier of Computer Science and Technology (FCST) 2008, pp.186-193, Nagasaki, Japan, Dec. 2008.
  • Daisuke Ohwada, Yuichi Okuyama, and Kenichi Kuroda, "Implementation of a Combined Autocorrelation Method for Real-time Tissue Elasticity Imaging on FPGA", IEEE 8th International Conference on Computer and Information Technology, pp.891-897, Sydney, Australia, July 2008.
  • Kaai Kojima, Yuichi Okuyama, and Kenichi Kuroda, "Arithmetic Precision of the Generalized Hebbian Algorithm for Hardware Implementation", IEEE 8th International Conference on Computer and Information Technology, pp.886-890, Sydney, Australia, July 2008.
  • A. Ben Abdallah, M. Masuda, A. Canedo, K. Kuroda, Natural Instruction Level Parallelism-aware Compiler for High-Performance Processor Architecture, To appear in the Journal of supercomputing, 2010.
  • A. Canedo, A. Ben@Abdallah, and M. Sowa, Efficient Compilation for Queue Size Constrained Queue Processors, The Journal of Parallel Computing, Vol.35, pp. 213-225, 2009.
  • A. Ben Abdallah, A. Canedo, T. Yoshinga, and M. Sowa, The QC-2 Parallel Queue Processor Architecture, Journal of Parallel and Distributed Computing, Vol. 68, No. 2, pp. 235-245, 2008

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